There has now been developed an electronic test technique, described in the ANSI/IEEE 1149.1 Test Access Port and Boundary Scan Architecture standard, which permits testing of devices on a circuit board embodying this architecture through a four-wire port on the board. Such testing is accomplished, in accordance with the ANSI/IEEE 1149.1 standard, by entering a known string of bits to the boundary scan devices. As the bits are entered, each bit is shifted into a corresponding boundary scan register within a device, which register is associated with a device's signal input or output pin. The shifting of a bit into a boundary scan register associated with a device input pin will cause a change in the status of the bit in one or more boundary scan registers, within the same device or other devices which are dependent on the signal at this input pin. The registers in the device are coupled in a serial chain so that by shifting out the bits from the chain of registers and comparing the shifted-out bit string to a known string produced under defect-free conditions, the operation of the boundary scan devices on the circuit board can be tested.
Complete testing of a circuit board requires not only that the devices be tested, but that the input/output connections to the board be tested as well. In the past, the circuit board input and output connections, which are typically made through separate pins of an edge connector carried by the board, were tested by applying test stimuli in parallel to the edge connector pins. Following application of the test stimuli, the response generated to the stimuli was sensed and analyzed. To simultaneously test both the devices on the circuit board and the input/output (I/O) connections, the stimuli applied to the edge connector pins had to be synchronized to the string of bits shifted through the boundary scan registers in the devices on the board. Such synchronization has required very complex test hardware and software which has increased the cost of testing circuit boards. Moreover, parallel test hardware is itself costly.
Thus, there is a need for a technique for simultaneously testing both the boundary scan devices on a circuit board and the circuit board I/O connections without the need for synchronization of the test signals.